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| author | Diego H <diego@symbioticeda.com> | 2019-12-12 13:40:05 -0600 |
|---|---|---|
| committer | Diego H <diego@symbioticeda.com> | 2019-12-12 13:40:05 -0600 |
| commit | ab6ac8327f28b2ba9530c81cdbb5091a1ef91032 (patch) | |
| tree | 9e2716d6d621eeeda85896b7b2993de517bb931a /techlibs/ice40/cells_map.v | |
| parent | 3a5a65829cc593965304537ddcb4d6d1d3e3ca8b (diff) | |
| parent | 2666482282421bb54213ba01054111eadc401373 (diff) | |
| download | yosys-ab6ac8327f28b2ba9530c81cdbb5091a1ef91032.tar.gz yosys-ab6ac8327f28b2ba9530c81cdbb5091a1ef91032.tar.bz2 yosys-ab6ac8327f28b2ba9530c81cdbb5091a1ef91032.zip | |
Merge https://github.com/YosysHQ/yosys into bram_xilinx
Diffstat (limited to 'techlibs/ice40/cells_map.v')
| -rw-r--r-- | techlibs/ice40/cells_map.v | 19 |
1 files changed, 0 insertions, 19 deletions
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v index 662423f0a..759549e30 100644 --- a/techlibs/ice40/cells_map.v +++ b/techlibs/ice40/cells_map.v @@ -61,22 +61,3 @@ module \$lut (A, Y); endgenerate endmodule `endif - -`ifndef NO_ADDER -module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3); - parameter LUT = 0; - SB_CARRY carry ( - .I0(A), - .I1(B), - .CI(CI), - .CO(CO) - ); - \$lut #( - .WIDTH(4), - .LUT(LUT) - ) lut ( - .A({I0,A,B,I3}), - .Y(O) - ); -endmodule -`endif |