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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 09:50:20 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 09:50:20 -0700 |
| commit | 295c18bd6b8d3fa503041904f7f7df392a4b5167 (patch) | |
| tree | 9a20c23d61a5c714ca8408c40d2e71345deff088 /techlibs/ice40/cells_sim.v | |
| parent | 4cc74346f11e96b9a2bce1c984c674a22771a00a (diff) | |
| parent | 6919c0f9b010c94a0a1a31cd788301e78a1bcbfb (diff) | |
| download | yosys-295c18bd6b8d3fa503041904f7f7df392a4b5167.tar.gz yosys-295c18bd6b8d3fa503041904f7f7df392a4b5167.tar.bz2 yosys-295c18bd6b8d3fa503041904f7f7df392a4b5167.zip | |
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
Diffstat (limited to 'techlibs/ice40/cells_sim.v')
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 23 |
1 files changed, 11 insertions, 12 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index ab04808f4..2a7487f6b 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -142,13 +142,16 @@ module SB_CARRY (output CO, input I0, I1, CI); endmodule (* abc_box_id = 1, lib_whitebox *) -module \$__ICE40_FULL_ADDER ( - (* abc_carry *) output CO, +module \$__ICE40_CARRY_WRAPPER ( + (* abc_carry *) + output CO, output O, - input A, - input B, - (* abc_carry *) input CI + input A, B, + (* abc_carry *) + input CI, + input I0, I3 ); + parameter LUT = 0; SB_CARRY carry ( .I0(A), .I1(B), @@ -156,16 +159,12 @@ module \$__ICE40_FULL_ADDER ( .CO(CO) ); SB_LUT4 #( - // I0: 1010 1010 1010 1010 - // I1: 1100 1100 1100 1100 - // I2: 1111 0000 1111 0000 - // I3: 1111 1111 0000 0000 - .LUT_INIT(16'b 0110_1001_1001_0110) + .LUT_INIT(LUT) ) adder ( - .I0(1'b0), + .I0(I0), .I1(A), .I2(B), - .I3(CI), + .I3(I3), .O(O) ); endmodule |