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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-18 15:45:25 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-18 15:45:25 -0700 |
| commit | 42e40dbd0a513d430ff0a463f9a80dedfbbf51f5 (patch) | |
| tree | 5cf69498d43b8d225e28cf5562f91c3a4a94f814 /techlibs/ice40/cells_sim.v | |
| parent | 09411dd996f75dbce22a6f6979b7d61b0dae24f7 (diff) | |
| parent | e66e8fb59d8443c8d55c1185d6b2ce889a35357d (diff) | |
| download | yosys-42e40dbd0a513d430ff0a463f9a80dedfbbf51f5.tar.gz yosys-42e40dbd0a513d430ff0a463f9a80dedfbbf51f5.tar.bz2 yosys-42e40dbd0a513d430ff0a463f9a80dedfbbf51f5.zip | |
Merge remote-tracking branch 'origin/master' into ice40dsp
Diffstat (limited to 'techlibs/ice40/cells_sim.v')
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 27 |
1 files changed, 25 insertions, 2 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index b746ba4e5..609facc93 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -127,7 +127,7 @@ endmodule // SiliconBlue Logic Cells -(* abc_box_id = 2, lib_whitebox *) +(* lib_whitebox *) module SB_LUT4 (output O, input I0, I1, I2, I3); parameter [15:0] LUT_INIT = 0; wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0]; @@ -136,11 +136,34 @@ module SB_LUT4 (output O, input I0, I1, I2, I3); assign O = I0 ? s1[1] : s1[0]; endmodule -(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *) +(* lib_whitebox *) module SB_CARRY (output CO, input I0, I1, CI); assign CO = (I0 && I1) || ((I0 || I1) && CI); endmodule +(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *) +module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI); + SB_CARRY carry ( + .I0(A), + .I1(B), + .CI(CI), + .CO(CO) + ); + SB_LUT4 #( + // I0: 1010 1010 1010 1010 + // I1: 1100 1100 1100 1100 + // I2: 1111 0000 1111 0000 + // I3: 1111 1111 0000 0000 + .LUT_INIT(16'b 0110_1001_1001_0110) + ) adder ( + .I0(1'b0), + .I1(A), + .I2(B), + .I3(CI), + .O(O) + ); +endmodule + // Positive Edge SiliconBlue FF Cells module SB_DFF (output `SB_DFF_REG, input C, D); |