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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-03 09:23:43 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-03 09:23:43 -0700 |
| commit | 9f44a7171528b90e85b2f33ef8823660fbd95609 (patch) | |
| tree | 7130be697055b80141a31eab869491d8436cf308 /techlibs/ice40/cells_sim.v | |
| parent | 2228cef62f8550f85b203752681e2abeef1197ea (diff) | |
| download | yosys-9f44a7171528b90e85b2f33ef8823660fbd95609.tar.gz yosys-9f44a7171528b90e85b2f33ef8823660fbd95609.tar.bz2 yosys-9f44a7171528b90e85b2f33ef8823660fbd95609.zip | |
Consistent with xilinx
Diffstat (limited to 'techlibs/ice40/cells_sim.v')
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index b5e10fb20..6897aeeb4 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -145,7 +145,7 @@ endmodule (* abc_box_id = 1, abc_flop, lib_whitebox *) module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D); -`ifndef ABC_MODEL +`ifndef _ABC always @(posedge C) Q <= D; `else |