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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 20:18:17 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 20:18:17 -0700 |
| commit | b7a48e3e0f49f09e12a2b394b62256a87c398dbc (patch) | |
| tree | 9667249b7e1ab86c264f44d0a2f03b326e2763fa /techlibs/ice40/cells_sim.v | |
| parent | c320abc3f490b09b21804581c2b386c30d186a1e (diff) | |
| parent | 33960dd3d84b628f6e5de45c112368dc80626457 (diff) | |
| download | yosys-b7a48e3e0f49f09e12a2b394b62256a87c398dbc.tar.gz yosys-b7a48e3e0f49f09e12a2b394b62256a87c398dbc.tar.bz2 yosys-b7a48e3e0f49f09e12a2b394b62256a87c398dbc.zip | |
Merge remote-tracking branch 'origin/master' into xc7dsp
Diffstat (limited to 'techlibs/ice40/cells_sim.v')
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 2205be27d..ab04808f4 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -141,8 +141,14 @@ module SB_CARRY (output CO, input I0, I1, CI); assign CO = (I0 && I1) || ((I0 || I1) && CI); endmodule -(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *) -module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI); +(* abc_box_id = 1, lib_whitebox *) +module \$__ICE40_FULL_ADDER ( + (* abc_carry *) output CO, + output O, + input A, + input B, + (* abc_carry *) input CI +); SB_CARRY carry ( .I0(A), .I1(B), |