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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-22 19:44:17 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-22 19:44:17 -0700 |
| commit | d54dceb547777ab4b489f66554d4c47e867424f9 (patch) | |
| tree | 8e60c03e2a40891b7a078717b8a3c931feb5ae83 /techlibs/ice40/cells_sim.v | |
| parent | bbf3ad90f59a5b548d263c81ca83ca8f93f1c238 (diff) | |
| parent | 6027549464bf91cee4d4bcbe9586e719dce78c80 (diff) | |
| download | yosys-d54dceb547777ab4b489f66554d4c47e867424f9.tar.gz yosys-d54dceb547777ab4b489f66554d4c47e867424f9.tar.bz2 yosys-d54dceb547777ab4b489f66554d4c47e867424f9.zip | |
Merge remote-tracking branch 'origin/xaig' into xc7mux
Diffstat (limited to 'techlibs/ice40/cells_sim.v')
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 031afa85c..317ae2c1f 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -127,7 +127,7 @@ endmodule // SiliconBlue Logic Cells -(* abc_box_id = 22, lib_whitebox *) +(* abc_box_id = 2, lib_whitebox *) module SB_LUT4 (output O, input I0, I1, I2, I3); parameter [15:0] LUT_INIT = 0; wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0]; @@ -136,7 +136,7 @@ module SB_LUT4 (output O, input I0, I1, I2, I3); assign O = I0 ? s1[1] : s1[0]; endmodule -(* abc_box_id = 21, abc_carry, lib_whitebox *) +(* abc_box_id = 1, abc_carry, lib_whitebox *) module SB_CARRY ((* abc_carry_out *) output CO, input I0, I1, (* abc_carry_in *) input CI); assign CO = (I0 && I1) || ((I0 || I1) && CI); endmodule |