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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-28 10:59:03 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-06-28 10:59:03 -0700 |
| commit | da5f83039527bf50af001671744f351988c3261a (patch) | |
| tree | 5af77e4b5c61a5d31b18cc807818d884b6884ec1 /techlibs/ice40/cells_sim.v | |
| parent | 74945dd738fca316f319771426646c4da327f662 (diff) | |
| parent | 38d8806bd74b9bb448c7488ec571e197fe2f96d6 (diff) | |
| download | yosys-da5f83039527bf50af001671744f351988c3261a.tar.gz yosys-da5f83039527bf50af001671744f351988c3261a.tar.bz2 yosys-da5f83039527bf50af001671744f351988c3261a.zip | |
Merge pull request #1098 from YosysHQ/xaig
"abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
Diffstat (limited to 'techlibs/ice40/cells_sim.v')
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index f9945b2b5..b746ba4e5 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -127,6 +127,7 @@ endmodule // SiliconBlue Logic Cells +(* abc_box_id = 2, lib_whitebox *) module SB_LUT4 (output O, input I0, I1, I2, I3); parameter [15:0] LUT_INIT = 0; wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0]; @@ -135,6 +136,7 @@ module SB_LUT4 (output O, input I0, I1, I2, I3); assign O = I0 ? s1[1] : s1[0]; endmodule +(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *) module SB_CARRY (output CO, input I0, I1, CI); assign CO = (I0 && I1) || ((I0 || I1) && CI); endmodule |