diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-11 21:13:40 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-11 21:13:40 -0700 |
| commit | 88d5185596a0cc8319658463a31b20644d90dd6b (patch) | |
| tree | 106f178d42a54403218f93cae2807d6e67981599 /techlibs/ice40/ice40_opt.cc | |
| parent | 282cc77604a9a855c303869321d4179790b0b64b (diff) | |
| parent | c851dc13108021834533094a8a3236da6d9e0161 (diff) | |
| download | yosys-88d5185596a0cc8319658463a31b20644d90dd6b.tar.gz yosys-88d5185596a0cc8319658463a31b20644d90dd6b.tar.bz2 yosys-88d5185596a0cc8319658463a31b20644d90dd6b.zip | |
Merge remote-tracking branch 'origin/master' into eddie/fix_1262
Diffstat (limited to 'techlibs/ice40/ice40_opt.cc')
| -rw-r--r-- | techlibs/ice40/ice40_opt.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index e492454fb..d5106b805 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -117,7 +117,7 @@ static void run_ice40_opts(Module *module) log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n", log_id(module), log_id(cell), log_signal(replacement_output)); cell->type = "$lut"; - cell->setPort("\\A", { RTLIL::S0, inbit[0], inbit[1], inbit[2] }); + cell->setPort("\\A", { State::S0, inbit[0], inbit[1], inbit[2] }); cell->setPort("\\Y", cell->getPort("\\O")); cell->unsetPort("\\B"); cell->unsetPort("\\CI"); |