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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-27 09:54:04 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-01-27 09:54:04 -0800 |
| commit | af8281d2f5e3945a8bb93dd7c7400aafb29af3b8 (patch) | |
| tree | 36afb76914bb8c2e4e03b1002aa696fd9d16768b /techlibs/ice40/ice40_opt.cc | |
| parent | 07a12ebd4ff12c8016809eacad4551246fa4b316 (diff) | |
| parent | b1787615514f84c83c27d08011427e90c9bd0f4a (diff) | |
| download | yosys-af8281d2f5e3945a8bb93dd7c7400aafb29af3b8.tar.gz yosys-af8281d2f5e3945a8bb93dd7c7400aafb29af3b8.tar.bz2 yosys-af8281d2f5e3945a8bb93dd7c7400aafb29af3b8.zip | |
Merge pull request #1656 from YosysHQ/eddie/ice40_abc9_warnings
ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
Diffstat (limited to 'techlibs/ice40/ice40_opt.cc')
| -rw-r--r-- | techlibs/ice40/ice40_opt.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index 9bee0444b..df10a2842 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -139,7 +139,8 @@ static void run_ice40_opts(Module *module) log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n", log_id(module), log_id(cell), log_signal(replacement_output)); cell->type = "$lut"; - cell->setPort("\\A", { cell->getPort("\\I0"), inbit[0], inbit[1], cell->getPort("\\I3") }); + auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3)); + cell->setPort("\\A", { cell->getPort("\\I0"), inbit[0], inbit[1], I3 }); cell->setPort("\\Y", cell->getPort("\\O")); cell->unsetPort("\\B"); cell->unsetPort("\\CI"); @@ -148,6 +149,7 @@ static void run_ice40_opts(Module *module) cell->unsetPort("\\CO"); cell->unsetPort("\\O"); cell->setParam("\\WIDTH", 4); + cell->unsetParam("\\I3_IS_CI"); } continue; } |