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author | Eddie Hung <eddie@fpgeh.com> | 2019-07-18 15:45:25 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-18 15:45:25 -0700 |
commit | 42e40dbd0a513d430ff0a463f9a80dedfbbf51f5 (patch) | |
tree | 5cf69498d43b8d225e28cf5562f91c3a4a94f814 /techlibs/ice40/ice40_unlut.cc | |
parent | 09411dd996f75dbce22a6f6979b7d61b0dae24f7 (diff) | |
parent | e66e8fb59d8443c8d55c1185d6b2ce889a35357d (diff) | |
download | yosys-42e40dbd0a513d430ff0a463f9a80dedfbbf51f5.tar.gz yosys-42e40dbd0a513d430ff0a463f9a80dedfbbf51f5.tar.bz2 yosys-42e40dbd0a513d430ff0a463f9a80dedfbbf51f5.zip |
Merge remote-tracking branch 'origin/master' into ice40dsp
Diffstat (limited to 'techlibs/ice40/ice40_unlut.cc')
-rw-r--r-- | techlibs/ice40/ice40_unlut.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/ice40/ice40_unlut.cc b/techlibs/ice40/ice40_unlut.cc index d16e6e6a3..f3f70ac1f 100644 --- a/techlibs/ice40/ice40_unlut.cc +++ b/techlibs/ice40/ice40_unlut.cc @@ -56,10 +56,10 @@ static void run_ice40_unlut(Module *module) cell->unsetParam("\\LUT_INIT"); cell->setPort("\\A", SigSpec({ - get_bit_or_zero(cell->getPort("\\I3")), - get_bit_or_zero(cell->getPort("\\I2")), + get_bit_or_zero(cell->getPort("\\I0")), get_bit_or_zero(cell->getPort("\\I1")), - get_bit_or_zero(cell->getPort("\\I0")) + get_bit_or_zero(cell->getPort("\\I2")), + get_bit_or_zero(cell->getPort("\\I3")) })); cell->setPort("\\Y", cell->getPort("\\O")[0]); cell->unsetPort("\\I0"); |