aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/ice40/synth_ice40.cc
diff options
context:
space:
mode:
authorEddie Hung <eddieh@ece.ubc.ca>2019-03-19 08:52:31 -0700
committerEddie Hung <eddieh@ece.ubc.ca>2019-03-19 08:52:31 -0700
commit02e8dc7ad2e13a43a310d311302c6db8168e6c11 (patch)
treeaf43bf9735fe47b09dbd8807c63fe451eb82aaba /techlibs/ice40/synth_ice40.cc
parent3e89cf68bdc4e9eeb55bd9450121f421bcdc554a (diff)
parent61f37706f93042c2d1f093dd9bfa717390911eb3 (diff)
downloadyosys-02e8dc7ad2e13a43a310d311302c6db8168e6c11.tar.gz
yosys-02e8dc7ad2e13a43a310d311302c6db8168e6c11.tar.bz2
yosys-02e8dc7ad2e13a43a310d311302c6db8168e6c11.zip
Merge https://github.com/YosysHQ/yosys into read_aiger
Diffstat (limited to 'techlibs/ice40/synth_ice40.cc')
-rw-r--r--techlibs/ice40/synth_ice40.cc33
1 files changed, 29 insertions, 4 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index f900453e8..8899bfcc4 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -79,6 +79,9 @@ struct SynthIce40Pass : public ScriptPass
log(" -nobram\n");
log(" do not use SB_RAM40_4K* cells in output netlist\n");
log("\n");
+ log(" -dsp\n");
+ log(" use iCE40 UltraPlus DSP cells for large arithmetic\n");
+ log("\n");
log(" -noabc\n");
log(" use built-in Yosys LUT techmapping instead of abc\n");
log("\n");
@@ -96,7 +99,7 @@ struct SynthIce40Pass : public ScriptPass
}
string top_opt, blif_file, edif_file, json_file;
- bool nocarry, nodffe, nobram, flatten, retime, relut, noabc, abc2, vpr;
+ bool nocarry, nodffe, nobram, dsp, flatten, retime, relut, noabc, abc2, vpr;
int min_ce_use;
void clear_flags() YS_OVERRIDE
@@ -109,6 +112,7 @@ struct SynthIce40Pass : public ScriptPass
nodffe = false;
min_ce_use = -1;
nobram = false;
+ dsp = false;
flatten = true;
retime = false;
relut = false;
@@ -181,6 +185,10 @@ struct SynthIce40Pass : public ScriptPass
nobram = true;
continue;
}
+ if (args[argidx] == "-dsp") {
+ dsp = true;
+ continue;
+ }
if (args[argidx] == "-noabc") {
noabc = true;
continue;
@@ -214,11 +222,11 @@ struct SynthIce40Pass : public ScriptPass
{
run("read_verilog -lib +/ice40/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
+ run("proc");
}
if (flatten && check_label("flatten", "(unless -noflatten)"))
{
- run("proc");
run("flatten");
run("tribuf -logic");
run("deminout");
@@ -226,13 +234,30 @@ struct SynthIce40Pass : public ScriptPass
if (check_label("coarse"))
{
- run("synth -lut 4 -run coarse");
+ run("opt_expr");
+ run("opt_clean");
+ run("check");
+ run("opt");
+ run("wreduce");
+ run("share");
+ run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
+ run("opt_expr");
+ run("opt_clean");
+ if (help_mode || dsp)
+ run("ice40_dsp", "(if -dsp)");
+ run("alumacc");
+ run("opt");
+ run("fsm");
+ run("opt -fast");
+ run("memory -nomap");
+ run("opt_clean");
}
if (!nobram && check_label("bram", "(skip if -nobram)"))
{
run("memory_bram -rules +/ice40/brams.txt");
run("techmap -map +/ice40/brams_map.v");
+ run("ice40_braminit");
}
if (check_label("map"))
@@ -282,7 +307,7 @@ struct SynthIce40Pass : public ScriptPass
run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
}
if (!noabc) {
- run("abc -lut 4", "(skip if -noabc)");
+ run("abc -dress -lut 4", "(skip if -noabc)");
}
run("clean");
if (relut || help_mode) {