Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff

abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *)

1 files changed, 20 insertions, 10 deletions

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 6e05ab0b2..27850b075 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -71,6 +71,9 @@ struct SynthIce40Pass : public ScriptPass
 		log("    -noflatten\n");
 		log("        do not flatten design before synthesis\n");
 		log("\n");
+		log("    -dff\n");
+		log("        run 'abc'/'abc9' with -dff option\n");
+		log("\n");
 		log("    -retime\n");
 		log("        run 'abc' with '-dff -D 1' options\n");
 		log("\n");
@@ -113,7 +116,7 @@ struct SynthIce40Pass : public ScriptPass
 	}
 
 	string top_opt, blif_file, edif_file, json_file, device_opt;
-	bool nocarry, nodffe, nobram, dsp, flatten, retime, noabc, abc2, vpr, abc9, flowmap;
+	bool nocarry, nodffe, nobram, dsp, flatten, retime, noabc, abc2, vpr, abc9, dff, flowmap;
 	int min_ce_use;
 
 	void clear_flags() YS_OVERRIDE
@@ -221,6 +224,10 @@ struct SynthIce40Pass : public ScriptPass
 				abc9 = true;
 				continue;
 			}
+			if (args[argidx] == "-dff") {
+				dff = true;
+				continue;
+			}
 			if (args[argidx] == "-device" && argidx+1 < args.size()) {
 				device_opt = args[++argidx];
 				continue;
@@ -354,7 +361,9 @@ struct SynthIce40Pass : public ScriptPass
 				run(stringf("dff2dffe -unmap-mince %d", min_ce_use));
 				run("simplemap t:$dff");
 			}
-			run("techmap -D NO_LUT -D NO_ADDER -map +/ice40/cells_map.v");
+			if ((abc9 && dff) || help_mode)
+				run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$__DFFS*", "(only if -abc9 and -dff");
+			run("techmap -map +/ice40/ff_map.v");
 			run("opt_expr -mux_undef");
 			run("simplemap");
 			run("ice40_ffinit");
@@ -378,7 +387,7 @@ struct SynthIce40Pass : public ScriptPass
 			}
 			if (!noabc) {
 				if (abc9) {
-					run("read_verilog " + define + " -icells -lib -specify +/abc9_model.v +/ice40/abc9_model.v");
+					run("read_verilog " + define + " -icells -lib -specify +/ice40/abc9_model.v");
 					std::string abc9_opts;
 					std::string k = "synth_ice40.abc9.W";
 					if (active_design && active_design->scratchpad.count(k))
@@ -387,24 +396,25 @@ struct SynthIce40Pass : public ScriptPass
 						k = stringf("synth_ice40.abc9.%s.W", device_opt.c_str());
 						abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str());
 					}
+					if (dff)
+						abc9_opts += " -dff";
 					run("abc9 " + abc9_opts);
 				}
 				else
-					run("abc -dress -lut 4", "(skip if -noabc)");
+					run(stringf("abc -dress -lut 4 %s", dff ? "-dff" : ""), "(skip if -noabc)");
 			}
 			run("ice40_wrapcarry -unwrap");
-			run("techmap -D NO_LUT -map +/ice40/cells_map.v");
+			run("techmap -map +/ice40/ff_map.v");
 			run("clean");
 			run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0");
 		}
 
 		if (check_label("map_cells"))
 		{
-			if (vpr)
-				run("techmap -D NO_LUT -map +/ice40/cells_map.v");
-			else
-				run("techmap -map +/ice40/cells_map.v", "(with -D NO_LUT in vpr mode)");
-
+			if (help_mode)
+				run("techmap -map +/ice40/cells_map.v", "(skip if -vpr)");
+			else if (!vpr)
+				run("techmap -map +/ice40/cells_map.v");
 			run("clean");
 		}