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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-28 11:09:42 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-28 11:09:42 -0700 |
| commit | 4ef26d4755d355e562a173c86d3eace100a266fe (patch) | |
| tree | 6d331a5b3fa83d9072c25f7825cacb4e3d30cea5 /techlibs/ice40/synth_ice40.cc | |
| parent | 1c79a32276ef4ae3601cb75e0ab05ba1afe4d385 (diff) | |
| parent | da5f83039527bf50af001671744f351988c3261a (diff) | |
| download | yosys-4ef26d4755d355e562a173c86d3eace100a266fe.tar.gz yosys-4ef26d4755d355e562a173c86d3eace100a266fe.tar.bz2 yosys-4ef26d4755d355e562a173c86d3eace100a266fe.zip | |
Merge remote-tracking branch 'origin/master' into xc7mux
Diffstat (limited to 'techlibs/ice40/synth_ice40.cc')
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index a782f00b9..9dd5d81f7 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -38,8 +38,8 @@ struct SynthIce40Pass : public ScriptPass log("This command runs synthesis for iCE40 FPGAs.\n"); log("\n"); log(" -device < hx | lp | u >\n"); - log(" optimise the synthesis netlist for the specified device.\n"); - log(" HX is the default target if no device argument specified.\n"); + log(" relevant only for '-abc9' flow, optimise timing for the specified device.\n"); + log(" default: hx\n"); log("\n"); log(" -top <module>\n"); log(" use the specified module as top module\n"); @@ -105,7 +105,6 @@ struct SynthIce40Pass : public ScriptPass log("\n"); } - string top_opt, blif_file, edif_file, json_file, abc, device_opt; bool nocarry, nodffe, nobram, dsp, flatten, retime, relut, noabc, abc2, vpr; int min_ce_use; |