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author | Pepijn de Vos <pepijndevos@gmail.com> | 2019-10-21 10:51:34 +0200 |
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committer | Pepijn de Vos <pepijndevos@gmail.com> | 2019-10-21 10:51:34 +0200 |
commit | 69fb3b8db21c8a50fa333bff3ef844af42729e0d (patch) | |
tree | 1a62aebe9ece22b19b4087f2c5cb5581b571c270 /techlibs/ice40/synth_ice40.cc | |
parent | 72323e11a4ee222c0ce928669d33333c46fb25aa (diff) | |
parent | fa989e59e5a37d804d8a82050e022b8f4b7070d8 (diff) | |
download | yosys-69fb3b8db21c8a50fa333bff3ef844af42729e0d.tar.gz yosys-69fb3b8db21c8a50fa333bff3ef844af42729e0d.tar.bz2 yosys-69fb3b8db21c8a50fa333bff3ef844af42729e0d.zip |
Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin
Diffstat (limited to 'techlibs/ice40/synth_ice40.cc')
-rw-r--r-- | techlibs/ice40/synth_ice40.cc | 26 |
1 files changed, 22 insertions, 4 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index c6de81bd9..b66c6bf57 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -238,7 +238,14 @@ struct SynthIce40Pass : public ScriptPass { if (check_label("begin")) { - run("read_verilog -icells -lib +/ice40/cells_sim.v"); + std::string define; + if (device_opt == "lp") + define = "-D ICE40_LP"; + else if (device_opt == "u") + define = "-D ICE40_U"; + else + define = "-D ICE40_HX"; + run("read_verilog " + define + " -lib +/ice40/cells_sim.v"); run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str())); run("proc"); } @@ -265,8 +272,18 @@ struct SynthIce40Pass : public ScriptPass run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4"); run("opt_expr"); run("opt_clean"); - if (help_mode || dsp) - run("ice40_dsp", "(if -dsp)"); + if (help_mode || dsp) { + run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 " + "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 " + "-D DSP_NAME=$__MUL16X16", "(if -dsp)"); + run("select a:mul2dsp", " (if -dsp)"); + run("setattr -unset mul2dsp", " (if -dsp)"); + run("opt_expr -fine", " (if -dsp)"); + run("wreduce", " (if -dsp)"); + run("select -clear", " (if -dsp)"); + run("ice40_dsp", " (if -dsp)"); + run("chtype -set $mul t:$__soft_mul", "(if -dsp)"); + } run("alumacc"); run("opt"); run("fsm"); @@ -332,6 +349,7 @@ struct SynthIce40Pass : public ScriptPass } if (!noabc) { if (abc == "abc9") { + run("read_verilog -icells -lib +/ice40/abc9_model.v"); int wire_delay; if (device_opt == "lp") wire_delay = 400; @@ -339,7 +357,7 @@ struct SynthIce40Pass : public ScriptPass wire_delay = 750; else wire_delay = 250; - run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)"); + run(abc + stringf(" -W %d -lut +/ice40/abc9_%s.lut -box +/ice40/abc9_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)"); } else run(abc + " -dress -lut 4", "(skip if -noabc)"); |