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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-03 09:23:43 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-03 09:23:43 -0700 |
| commit | 9f44a7171528b90e85b2f33ef8823660fbd95609 (patch) | |
| tree | 7130be697055b80141a31eab869491d8436cf308 /techlibs/ice40/synth_ice40.cc | |
| parent | 2228cef62f8550f85b203752681e2abeef1197ea (diff) | |
| download | yosys-9f44a7171528b90e85b2f33ef8823660fbd95609.tar.gz yosys-9f44a7171528b90e85b2f33ef8823660fbd95609.tar.bz2 yosys-9f44a7171528b90e85b2f33ef8823660fbd95609.zip | |
Consistent with xilinx
Diffstat (limited to 'techlibs/ice40/synth_ice40.cc')
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 168161a90..5afa042b0 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass { if (check_label("begin")) { - run("read_verilog -lib -D ABC_MODEL +/ice40/cells_sim.v"); + run("read_verilog -lib -D_ABC +/ice40/cells_sim.v"); run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str())); run("proc"); } @@ -334,7 +334,7 @@ struct SynthIce40Pass : public ScriptPass if (abc == "abc9") run(abc + stringf(" -dress -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)"); else - run(abc + " -lut 4", "(skip if -noabc)"); + run(abc + " -dress -lut 4", "(skip if -noabc)"); } run("clean"); if (relut || help_mode) { |