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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-08 10:53:38 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-08 10:53:38 -0700 |
| commit | 9fd2ddb14c0f7c40f6ed01a5db61cb6b327d877f (patch) | |
| tree | 526027efe405ddd8741558d150a341478d269d1f /techlibs/ice40/synth_ice40.cc | |
| parent | 472b5d33a624c2e414ce733c1cda0b97bce24094 (diff) | |
| parent | a5ac33f230b5dd20273f6636e5b573ef0478b8f9 (diff) | |
| download | yosys-9fd2ddb14c0f7c40f6ed01a5db61cb6b327d877f.tar.gz yosys-9fd2ddb14c0f7c40f6ed01a5db61cb6b327d877f.tar.bz2 yosys-9fd2ddb14c0f7c40f6ed01a5db61cb6b327d877f.zip | |
Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9
Rename abc_* names/attributes to more precisely be abc9_*
Diffstat (limited to 'techlibs/ice40/synth_ice40.cc')
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 2e4684c19..b66c6bf57 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -349,7 +349,7 @@ struct SynthIce40Pass : public ScriptPass } if (!noabc) { if (abc == "abc9") { - run("read_verilog -icells -lib +/ice40/abc_model.v"); + run("read_verilog -icells -lib +/ice40/abc9_model.v"); int wire_delay; if (device_opt == "lp") wire_delay = 400; @@ -357,7 +357,7 @@ struct SynthIce40Pass : public ScriptPass wire_delay = 750; else wire_delay = 250; - run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)"); + run(abc + stringf(" -W %d -lut +/ice40/abc9_%s.lut -box +/ice40/abc9_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)"); } else run(abc + " -dress -lut 4", "(skip if -noabc)"); |