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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-19 21:09:55 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-19 21:09:55 -0700 |
| commit | af4652522fd01aaec84664e65d7fe1474c578c49 (patch) | |
| tree | b1831952243702bc1b178cf1ae52d4ab23f0f18a /techlibs/ice40/synth_ice40.cc | |
| parent | 59c993e4372df1624b538bd12aee96381c874f6f (diff) | |
| download | yosys-af4652522fd01aaec84664e65d7fe1474c578c49.tar.gz yosys-af4652522fd01aaec84664e65d7fe1474c578c49.tar.bz2 yosys-af4652522fd01aaec84664e65d7fe1474c578c49.zip | |
ABC_FLOPS -> ABC_MODEL -- only whitebox if ABC_MODEL set
Diffstat (limited to 'techlibs/ice40/synth_ice40.cc')
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index d5d354701..7cedecdff 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass { if (check_label("begin")) { - run("read_verilog -wb -D ABC_FLOPS +/ice40/cells_sim.v"); + run("read_verilog -wb -D ABC_MODEL +/ice40/cells_sim.v"); run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str())); run("proc"); } |