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| author | Tim 'mithro' Ansell <me@mith.ro> | 2018-04-18 16:48:05 -0700 |
|---|---|---|
| committer | Tim 'mithro' Ansell <me@mith.ro> | 2018-04-18 16:55:12 -0700 |
| commit | d6bdefd2e93ad25fd63103d4b76a5573debc6d03 (patch) | |
| tree | 544397a34a4262465eb12b350469a9f63c0b19aa /techlibs/ice40/synth_ice40.cc | |
| parent | ca39e493ba78e7a4eaf3f0876321f892cce20f65 (diff) | |
| download | yosys-d6bdefd2e93ad25fd63103d4b76a5573debc6d03.tar.gz yosys-d6bdefd2e93ad25fd63103d4b76a5573debc6d03.tar.bz2 yosys-d6bdefd2e93ad25fd63103d4b76a5573debc6d03.zip | |
Improving vpr output support.
* Support output BLIF for Xilinx architectures.
* Support using .names in BLIF for Xilinx architectures.
* Use the same `NO_LUT` define in both `synth_ice40` and
`synth_xilinx`.
Diffstat (limited to 'techlibs/ice40/synth_ice40.cc')
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 10a1d600b..177581d53 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -219,7 +219,7 @@ struct SynthIce40Pass : public ScriptPass run("dffsr2dff"); if (!nodffe) run("dff2dffe -direct-match $_DFF_*"); - run("techmap -D NO_SB_LUT4 -map +/ice40/cells_map.v"); + run("techmap -D NO_LUT -map +/ice40/cells_map.v"); run("opt_expr -mux_undef"); run("simplemap"); run("ice40_ffinit"); @@ -241,9 +241,9 @@ struct SynthIce40Pass : public ScriptPass if (check_label("map_cells")) { if (vpr) - run("techmap -D NO_SB_LUT4 -map +/ice40/cells_map.v"); + run("techmap -D NO_LUT -map +/ice40/cells_map.v"); else - run("techmap -map +/ice40/cells_map.v", "(with -D NO_SB_LUT4 in vpr mode)"); + run("techmap -map +/ice40/cells_map.v", "(with -D NO_LUT in vpr mode)"); run("clean"); } |