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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-27 12:29:28 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-27 12:29:28 -0800 |
| commit | f2576c096cedf0974f237530a9d50e250bf117a3 (patch) | |
| tree | 3f5a0653615a125b0b51a2b135f5ac6d0b95794b /techlibs/ice40/synth_ice40.cc | |
| parent | b0605128b633f64b07107ba3a673f406e96d42ad (diff) | |
| parent | 9009b76a69b9e867f69295a8e555305925e83aeb (diff) | |
| download | yosys-f2576c096cedf0974f237530a9d50e250bf117a3.tar.gz yosys-f2576c096cedf0974f237530a9d50e250bf117a3.tar.bz2 yosys-f2576c096cedf0974f237530a9d50e250bf117a3.zip | |
Merge branch 'eddie/abc9_refactor' into eddie/abc9_required
Diffstat (limited to 'techlibs/ice40/synth_ice40.cc')
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 121bcff1f..d92e40726 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -273,7 +273,8 @@ struct SynthIce40Pass : public ScriptPass run("opt_expr"); run("opt_clean"); if (help_mode || dsp) { - run("memory_dff"); + run("memory_dff"); // ice40_dsp will merge registers, reserve memory port registers first + run("wreduce t:$mul"); run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 " "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 " "-D DSP_NAME=$__MUL16X16", "(if -dsp)"); |