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| author | whitequark <whitequark@whitequark.org> | 2019-08-18 08:04:26 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-18 08:04:26 +0000 |
| commit | 98a54353b7d893752d856b3726853d4921c6aa1f (patch) | |
| tree | e1a9537620e8a7dbc213044beea3d7e71173c410 /techlibs/ice40/tests/test_arith.ys | |
| parent | 2a78a1fd00fe66972885117efb1ac6a8b095f061 (diff) | |
| parent | 101235400caeb4ec019311dfb96100b770060c92 (diff) | |
| download | yosys-98a54353b7d893752d856b3726853d4921c6aa1f.tar.gz yosys-98a54353b7d893752d856b3726853d4921c6aa1f.tar.bz2 yosys-98a54353b7d893752d856b3726853d4921c6aa1f.zip | |
Merge pull request #1290 from YosysHQ/eddie/pr1266_again
Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER (retry)
Diffstat (limited to 'techlibs/ice40/tests/test_arith.ys')
| -rw-r--r-- | techlibs/ice40/tests/test_arith.ys | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/techlibs/ice40/tests/test_arith.ys b/techlibs/ice40/tests/test_arith.ys index 160c767fb..ddb80b700 100644 --- a/techlibs/ice40/tests/test_arith.ys +++ b/techlibs/ice40/tests/test_arith.ys @@ -1,6 +1,5 @@ read_verilog test_arith.v synth_ice40 -techmap -map ../cells_sim.v rename test gate read_verilog test_arith.v @@ -8,3 +7,11 @@ rename test gold miter -equiv -flatten -make_outputs gold gate miter sat -verify -prove trigger 0 -show-ports miter + +synth_ice40 -top gate + +read_verilog test_arith.v +rename test gold + +miter -equiv -flatten -make_outputs gold gate miter +sat -verify -prove trigger 0 -show-ports miter |