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| author | David Shah <davey1576@gmail.com> | 2019-08-10 17:14:48 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-10 17:14:48 +0100 |
| commit | f9020ce2b35f2fc205fc71cb095efce1a24fd86d (patch) | |
| tree | 73ac462dd723cc389070cea893ddc9c1998339a2 /techlibs/ice40/tests/test_arith.ys | |
| parent | f54bf1631ff37a83733c162e6ebd188c1d5ea18f (diff) | |
| download | yosys-f9020ce2b35f2fc205fc71cb095efce1a24fd86d.tar.gz yosys-f9020ce2b35f2fc205fc71cb095efce1a24fd86d.tar.bz2 yosys-f9020ce2b35f2fc205fc71cb095efce1a24fd86d.zip | |
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"
Diffstat (limited to 'techlibs/ice40/tests/test_arith.ys')
| -rw-r--r-- | techlibs/ice40/tests/test_arith.ys | 9 |
1 files changed, 1 insertions, 8 deletions
diff --git a/techlibs/ice40/tests/test_arith.ys b/techlibs/ice40/tests/test_arith.ys index ddb80b700..160c767fb 100644 --- a/techlibs/ice40/tests/test_arith.ys +++ b/techlibs/ice40/tests/test_arith.ys @@ -1,5 +1,6 @@ read_verilog test_arith.v synth_ice40 +techmap -map ../cells_sim.v rename test gate read_verilog test_arith.v @@ -7,11 +8,3 @@ rename test gold miter -equiv -flatten -make_outputs gold gate miter sat -verify -prove trigger 0 -show-ports miter - -synth_ice40 -top gate - -read_verilog test_arith.v -rename test gold - -miter -equiv -flatten -make_outputs gold gate miter -sat -verify -prove trigger 0 -show-ports miter |