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| author | Clifford Wolf <clifford@clifford.at> | 2015-04-24 08:32:07 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-04-24 08:32:07 +0200 |
| commit | 308a59aa181103ea11aef26e43c9ae6993ad0040 (patch) | |
| tree | ccc6c83376ef52db6bc50744c963657443455fc2 /techlibs/ice40/tests/test_bram.v | |
| parent | d6f7698f591aa1957e263e13b66d0d808cf5a478 (diff) | |
| download | yosys-308a59aa181103ea11aef26e43c9ae6993ad0040.tar.gz yosys-308a59aa181103ea11aef26e43c9ae6993ad0040.tar.bz2 yosys-308a59aa181103ea11aef26e43c9ae6993ad0040.zip | |
iCE40 bram tests and fixes
Diffstat (limited to 'techlibs/ice40/tests/test_bram.v')
| -rw-r--r-- | techlibs/ice40/tests/test_bram.v | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/techlibs/ice40/tests/test_bram.v b/techlibs/ice40/tests/test_bram.v new file mode 100644 index 000000000..d26df7572 --- /dev/null +++ b/techlibs/ice40/tests/test_bram.v @@ -0,0 +1,19 @@ +module bram #( + parameter ABITS = 8, DBITS = 8 +) ( + input clk, + + input [ABITS-1:0] WR_ADDR, + input [DBITS-1:0] WR_DATA, + input WR_EN, + + input [ABITS-1:0] RD_ADDR, + output reg [DBITS-1:0] RD_DATA +); + reg [DBITS-1:0] memory [0:2**ABITS-1]; + + always @(posedge clk) begin + if (WR_EN) memory[WR_ADDR] <= WR_DATA; + RD_DATA <= memory[RD_ADDR]; + end +endmodule |