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| author | Clifford Wolf <clifford@clifford.at> | 2015-04-25 20:44:51 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-04-25 20:44:51 +0200 |
| commit | b4d7a590e8d6ab5034adf9a34c1ef4a3b3c2a708 (patch) | |
| tree | 901093533554f591015be7d0853606894793f8a4 /techlibs/ice40/tests/test_bram.v | |
| parent | 4cc44005145310e544d0eb7bfd6b1a2ecdf7f1a7 (diff) | |
| download | yosys-b4d7a590e8d6ab5034adf9a34c1ef4a3b3c2a708.tar.gz yosys-b4d7a590e8d6ab5034adf9a34c1ef4a3b3c2a708.tar.bz2 yosys-b4d7a590e8d6ab5034adf9a34c1ef4a3b3c2a708.zip | |
initialized iCE40 brams (mode 0)
Diffstat (limited to 'techlibs/ice40/tests/test_bram.v')
| -rw-r--r-- | techlibs/ice40/tests/test_bram.v | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/techlibs/ice40/tests/test_bram.v b/techlibs/ice40/tests/test_bram.v index d26df7572..a625b6b66 100644 --- a/techlibs/ice40/tests/test_bram.v +++ b/techlibs/ice40/tests/test_bram.v @@ -1,5 +1,6 @@ module bram #( - parameter ABITS = 8, DBITS = 8 + parameter ABITS = 8, DBITS = 8, + parameter INIT_ADDR = 0, INIT_DATA = 0 ) ( input clk, @@ -12,6 +13,11 @@ module bram #( ); reg [DBITS-1:0] memory [0:2**ABITS-1]; + initial begin + if (INIT_ADDR || INIT_DATA) + memory[INIT_ADDR] <= INIT_DATA; + end + always @(posedge clk) begin if (WR_EN) memory[WR_ADDR] <= WR_DATA; RD_DATA <= memory[RD_ADDR]; |