diff options
| author | Clifford Wolf <clifford@clifford.at> | 2015-04-24 15:38:11 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-04-24 15:38:11 +0200 |
| commit | 687f5a5b12b41c4e26c9e5b8d3815c268a7ff7be (patch) | |
| tree | f8eb9efb98ab35fe8df26d927eb70c85f70682ab /techlibs/ice40/tests/test_bram_tb.v | |
| parent | 308a59aa181103ea11aef26e43c9ae6993ad0040 (diff) | |
| download | yosys-687f5a5b12b41c4e26c9e5b8d3815c268a7ff7be.tar.gz yosys-687f5a5b12b41c4e26c9e5b8d3815c268a7ff7be.tar.bz2 yosys-687f5a5b12b41c4e26c9e5b8d3815c268a7ff7be.zip | |
iCE40 bram progress
Diffstat (limited to 'techlibs/ice40/tests/test_bram_tb.v')
| -rw-r--r-- | techlibs/ice40/tests/test_bram_tb.v | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/techlibs/ice40/tests/test_bram_tb.v b/techlibs/ice40/tests/test_bram_tb.v index b0ac0402a..5d9f92228 100644 --- a/techlibs/ice40/tests/test_bram_tb.v +++ b/techlibs/ice40/tests/test_bram_tb.v @@ -79,14 +79,14 @@ module bram_tb #( clk <= 0; for (i = 0; i < 512; i = i+1) begin - WR_DATA <= xorshift64_state; + WR_DATA = xorshift64_state; xorshift64_next; - WR_ADDR <= getaddr(i < 256 ? i[7:4] : xorshift64_state[63:60]); + WR_ADDR = getaddr(i < 256 ? i[7:4] : xorshift64_state[63:60]); xorshift64_next; - RD_ADDR <= getaddr(i < 256 ? i[3:0] : xorshift64_state[59:56]); - WR_EN <= xorshift64_state[55]; + RD_ADDR = getaddr(i < 256 ? i[3:0] : xorshift64_state[59:56]); + WR_EN = xorshift64_state[55] && (WR_ADDR != RD_ADDR); xorshift64_next; #1; clk <= 1; @@ -98,7 +98,9 @@ module bram_tb #( for (j = 0; j < DBITS; j = j+1) expected_rd_masked[j] = expected_rd[j] !== 1'bx ? expected_rd[j] : RD_DATA[j]; - $display("#OUT# %3d | WA=%x WD=%x WE=%x | RA=%x RD=%x (%x) | %s", i, WR_ADDR, WR_DATA, WR_EN, RD_ADDR, RD_DATA, expected_rd, expected_rd_masked === RD_DATA ? "ok" : "ERROR"); + $display("#OUT# %3d | WA=%x WD=%x WE=%x | RA=%x RD=%x (%x) | %s", + i, WR_ADDR, WR_DATA, WR_EN, RD_ADDR, RD_DATA, expected_rd, + expected_rd_masked === RD_DATA ? "ok" : "ERROR"); if (expected_rd_masked !== RD_DATA) begin -> error; end end end |