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| author | Clifford Wolf <clifford@clifford.at> | 2015-04-25 20:44:51 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-04-25 20:44:51 +0200 |
| commit | b4d7a590e8d6ab5034adf9a34c1ef4a3b3c2a708 (patch) | |
| tree | 901093533554f591015be7d0853606894793f8a4 /techlibs/ice40/tests/test_bram_tb.v | |
| parent | 4cc44005145310e544d0eb7bfd6b1a2ecdf7f1a7 (diff) | |
| download | yosys-b4d7a590e8d6ab5034adf9a34c1ef4a3b3c2a708.tar.gz yosys-b4d7a590e8d6ab5034adf9a34c1ef4a3b3c2a708.tar.bz2 yosys-b4d7a590e8d6ab5034adf9a34c1ef4a3b3c2a708.zip | |
initialized iCE40 brams (mode 0)
Diffstat (limited to 'techlibs/ice40/tests/test_bram_tb.v')
| -rw-r--r-- | techlibs/ice40/tests/test_bram_tb.v | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/techlibs/ice40/tests/test_bram_tb.v b/techlibs/ice40/tests/test_bram_tb.v index ade53db03..abf953053 100644 --- a/techlibs/ice40/tests/test_bram_tb.v +++ b/techlibs/ice40/tests/test_bram_tb.v @@ -1,5 +1,6 @@ module bram_tb #( - parameter ABITS = 8, DBITS = 8 + parameter ABITS = 8, DBITS = 8, + parameter INIT_ADDR = 0, INIT_DATA = 0 ); reg clk; reg [ABITS-1:0] WR_ADDR; @@ -63,6 +64,9 @@ module bram_tb #( // $dumpfile("testbench.vcd"); // $dumpvars(0, bram_tb); + if (INIT_ADDR || INIT_DATA) + memory[INIT_ADDR] <= INIT_DATA; + xorshift64_next; xorshift64_next; xorshift64_next; @@ -85,7 +89,7 @@ module bram_tb #( WR_ADDR = getaddr(i < 256 ? i[7:4] : xorshift64_state[63:60]); xorshift64_next; - RD_ADDR = getaddr(i < 256 ? i[3:0] : xorshift64_state[59:56]); + RD_ADDR = i == 0 ? INIT_ADDR : getaddr(i < 256 ? i[3:0] : xorshift64_state[59:56]); WR_EN = xorshift64_state[55] && ((WR_ADDR & 'hff) != (RD_ADDR & 'hff)); xorshift64_next; |