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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-19 08:52:31 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-19 08:52:31 -0700 |
| commit | 02e8dc7ad2e13a43a310d311302c6db8168e6c11 (patch) | |
| tree | af43bf9735fe47b09dbd8807c63fe451eb82aaba /techlibs/ice40/tests/test_dsp_model.sh | |
| parent | 3e89cf68bdc4e9eeb55bd9450121f421bcdc554a (diff) | |
| parent | 61f37706f93042c2d1f093dd9bfa717390911eb3 (diff) | |
| download | yosys-02e8dc7ad2e13a43a310d311302c6db8168e6c11.tar.gz yosys-02e8dc7ad2e13a43a310d311302c6db8168e6c11.tar.bz2 yosys-02e8dc7ad2e13a43a310d311302c6db8168e6c11.zip | |
Merge https://github.com/YosysHQ/yosys into read_aiger
Diffstat (limited to 'techlibs/ice40/tests/test_dsp_model.sh')
| -rw-r--r-- | techlibs/ice40/tests/test_dsp_model.sh | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/techlibs/ice40/tests/test_dsp_model.sh b/techlibs/ice40/tests/test_dsp_model.sh new file mode 100644 index 000000000..1bc0cc688 --- /dev/null +++ b/techlibs/ice40/tests/test_dsp_model.sh @@ -0,0 +1,11 @@ +#!/bin/bash +set -ex +sed 's/SB_MAC16/SB_MAC16_UUT/; /SB_MAC16_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v +cat /opt/lscc/iCEcube2.2017.01/verilog/sb_ice_syn.v > test_dsp_model_ref.v +for tb in testbench \ + testbench_comb_8x8_A testbench_comb_8x8_B testbench_comb_16x16 \ + testbench_seq_16x16_A testbench_seq_16x16_B +do + iverilog -s $tb -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v + vvp -N ./test_dsp_model +done |