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| author | Clifford Wolf <clifford@clifford.at> | 2019-02-20 12:55:20 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-02-20 12:55:20 +0100 |
| commit | 7bf4e4a1855df442191e3d1cc28eeda7e01d051c (patch) | |
| tree | bba2d506d149ca2b17c37365cba4f6f862a51d64 /techlibs/ice40/tests/test_dsp_model.sh | |
| parent | dca65d83a0037539464d303ea8751a3e06a92e03 (diff) | |
| download | yosys-7bf4e4a1855df442191e3d1cc28eeda7e01d051c.tar.gz yosys-7bf4e4a1855df442191e3d1cc28eeda7e01d051c.tar.bz2 yosys-7bf4e4a1855df442191e3d1cc28eeda7e01d051c.zip | |
Improve iCE40 SB_MAC16 model
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'techlibs/ice40/tests/test_dsp_model.sh')
| -rw-r--r-- | techlibs/ice40/tests/test_dsp_model.sh | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/techlibs/ice40/tests/test_dsp_model.sh b/techlibs/ice40/tests/test_dsp_model.sh index ad079b2b6..1bc0cc688 100644 --- a/techlibs/ice40/tests/test_dsp_model.sh +++ b/techlibs/ice40/tests/test_dsp_model.sh @@ -2,5 +2,10 @@ set -ex sed 's/SB_MAC16/SB_MAC16_UUT/; /SB_MAC16_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v cat /opt/lscc/iCEcube2.2017.01/verilog/sb_ice_syn.v > test_dsp_model_ref.v -iverilog -s testbench -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v -./test_dsp_model +for tb in testbench \ + testbench_comb_8x8_A testbench_comb_8x8_B testbench_comb_16x16 \ + testbench_seq_16x16_A testbench_seq_16x16_B +do + iverilog -s $tb -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v + vvp -N ./test_dsp_model +done |