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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-23 09:56:58 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-07-23 09:56:58 -0700 |
| commit | a66f17b6a78af8f6989235f0c72d5548b0560a58 (patch) | |
| tree | ad135d83bf75e72b65e3136b4f6746c1f9cafab3 /techlibs/ice40/tests/test_dsp_model.sh | |
| parent | be3d9c8eaac637d9fe11f750e163680639543fdd (diff) | |
| parent | 80884d6f7bd10d79e89ad3893ae557aa64af9742 (diff) | |
| download | yosys-a66f17b6a78af8f6989235f0c72d5548b0560a58.tar.gz yosys-a66f17b6a78af8f6989235f0c72d5548b0560a58.tar.bz2 yosys-a66f17b6a78af8f6989235f0c72d5548b0560a58.zip | |
Merge pull request #1212 from YosysHQ/eddie/signed_ice40_dsp
ice40: Fix SB_MAC16 sim model for signed modes
Diffstat (limited to 'techlibs/ice40/tests/test_dsp_model.sh')
| -rw-r--r-- | techlibs/ice40/tests/test_dsp_model.sh | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/techlibs/ice40/tests/test_dsp_model.sh b/techlibs/ice40/tests/test_dsp_model.sh index 1bc0cc688..1e564d1b2 100644 --- a/techlibs/ice40/tests/test_dsp_model.sh +++ b/techlibs/ice40/tests/test_dsp_model.sh @@ -1,10 +1,15 @@ #!/bin/bash set -ex sed 's/SB_MAC16/SB_MAC16_UUT/; /SB_MAC16_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v -cat /opt/lscc/iCEcube2.2017.01/verilog/sb_ice_syn.v > test_dsp_model_ref.v +if [ ! -f "test_dsp_model_ref.v" ]; then + cat /opt/lscc/iCEcube2.2017.01/verilog/sb_ice_syn.v > test_dsp_model_ref.v +fi for tb in testbench \ testbench_comb_8x8_A testbench_comb_8x8_B testbench_comb_16x16 \ - testbench_seq_16x16_A testbench_seq_16x16_B + testbench_seq_16x16_A testbench_seq_16x16_B \ + testbench_comb_8x8_A_signedA testbench_comb_8x8_A_signedB testbench_comb_8x8_A_signedAB \ + testbench_comb_8x8_B_signedA testbench_comb_8x8_B_signedB testbench_comb_8x8_B_signedAB \ + testbench_comb_16x16_signedA testbench_comb_16x16_signedB testbench_comb_16x16_signedAB do iverilog -s $tb -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v vvp -N ./test_dsp_model |