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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-21 11:23:00 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-21 11:23:00 -0800 |
| commit | a8803a1519ce9191c43cd9a0f09d6c3ae99666e9 (patch) | |
| tree | 88dcf42e2eb5121441fa95ea9146bc8b217b0160 /techlibs/ice40/tests/test_dsp_model.sh | |
| parent | 5994382a20a0b7e890d22d032eecb39b61e0b3ce (diff) | |
| parent | d55790909c3b4244889d092c8eae630c7efd1aee (diff) | |
| download | yosys-a8803a1519ce9191c43cd9a0f09d6c3ae99666e9.tar.gz yosys-a8803a1519ce9191c43cd9a0f09d6c3ae99666e9.tar.bz2 yosys-a8803a1519ce9191c43cd9a0f09d6c3ae99666e9.zip | |
Merge remote-tracking branch 'origin/master' into xaig
Diffstat (limited to 'techlibs/ice40/tests/test_dsp_model.sh')
| -rw-r--r-- | techlibs/ice40/tests/test_dsp_model.sh | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/techlibs/ice40/tests/test_dsp_model.sh b/techlibs/ice40/tests/test_dsp_model.sh new file mode 100644 index 000000000..1bc0cc688 --- /dev/null +++ b/techlibs/ice40/tests/test_dsp_model.sh @@ -0,0 +1,11 @@ +#!/bin/bash +set -ex +sed 's/SB_MAC16/SB_MAC16_UUT/; /SB_MAC16_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v +cat /opt/lscc/iCEcube2.2017.01/verilog/sb_ice_syn.v > test_dsp_model_ref.v +for tb in testbench \ + testbench_comb_8x8_A testbench_comb_8x8_B testbench_comb_16x16 \ + testbench_seq_16x16_A testbench_seq_16x16_B +do + iverilog -s $tb -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v + vvp -N ./test_dsp_model +done |