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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-08 07:58:11 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-08 07:58:11 -0700 |
| commit | 61d7f1997ba7e3098acc25694accdd0ff25b8ab1 (patch) | |
| tree | 9f61784ace2ff54c0f6cd3705804f13af41f964c /techlibs/ice40/tests | |
| parent | 3414ee1e3fe37d4bf383621542828d4fc8fc987f (diff) | |
| parent | 8bf45f34c4d7143c58acde2544603cde443ad142 (diff) | |
| download | yosys-61d7f1997ba7e3098acc25694accdd0ff25b8ab1.tar.gz yosys-61d7f1997ba7e3098acc25694accdd0ff25b8ab1.tar.bz2 yosys-61d7f1997ba7e3098acc25694accdd0ff25b8ab1.zip | |
Merge pull request #1266 from YosysHQ/eddie/ice40_full_adder
Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER
Diffstat (limited to 'techlibs/ice40/tests')
| -rw-r--r-- | techlibs/ice40/tests/test_arith.ys | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/techlibs/ice40/tests/test_arith.ys b/techlibs/ice40/tests/test_arith.ys index 160c767fb..ddb80b700 100644 --- a/techlibs/ice40/tests/test_arith.ys +++ b/techlibs/ice40/tests/test_arith.ys @@ -1,6 +1,5 @@ read_verilog test_arith.v synth_ice40 -techmap -map ../cells_sim.v rename test gate read_verilog test_arith.v @@ -8,3 +7,11 @@ rename test gold miter -equiv -flatten -make_outputs gold gate miter sat -verify -prove trigger 0 -show-ports miter + +synth_ice40 -top gate + +read_verilog test_arith.v +rename test gold + +miter -equiv -flatten -make_outputs gold gate miter +sat -verify -prove trigger 0 -show-ports miter |