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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-08-09 09:46:37 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-08-09 09:46:37 +0200 |
| commit | 7a860c562323b8279cdbb8626a47ac8466c78b4c (patch) | |
| tree | d713b5c04ab34aadcbd310237a8cc46951f83e37 /techlibs/ice40/tests | |
| parent | 8a3329871ba7bab98982a101327b8375cd73344d (diff) | |
| parent | ac2fc3a144fe1094bedcc6b3fda8a498ad43ae76 (diff) | |
| download | yosys-7a860c562323b8279cdbb8626a47ac8466c78b4c.tar.gz yosys-7a860c562323b8279cdbb8626a47ac8466c78b4c.tar.bz2 yosys-7a860c562323b8279cdbb8626a47ac8466c78b4c.zip | |
Merge remote-tracking branch 'upstream/master' into efinix
Diffstat (limited to 'techlibs/ice40/tests')
| -rw-r--r-- | techlibs/ice40/tests/test_arith.ys | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/techlibs/ice40/tests/test_arith.ys b/techlibs/ice40/tests/test_arith.ys index 160c767fb..ddb80b700 100644 --- a/techlibs/ice40/tests/test_arith.ys +++ b/techlibs/ice40/tests/test_arith.ys @@ -1,6 +1,5 @@ read_verilog test_arith.v synth_ice40 -techmap -map ../cells_sim.v rename test gate read_verilog test_arith.v @@ -8,3 +7,11 @@ rename test gold miter -equiv -flatten -make_outputs gold gate miter sat -verify -prove trigger 0 -show-ports miter + +synth_ice40 -top gate + +read_verilog test_arith.v +rename test gold + +miter -equiv -flatten -make_outputs gold gate miter +sat -verify -prove trigger 0 -show-ports miter |