More iCE40 bram improvements

2 files changed, 4 insertions, 4 deletions

diff --git a/techlibs/ice40/tests/test_bram.sh b/techlibs/ice40/tests/test_bram.sh
index d24c50bc5..a8be04c4e 100644
--- a/techlibs/ice40/tests/test_bram.sh
+++ b/techlibs/ice40/tests/test_bram.sh
@@ -8,10 +8,10 @@ for dbits in 2 4 8 16 24 32; do
 	sed -e "s/ABITS = ./ABITS = $abits/g; s/DBITS = ./DBITS = $dbits/g;" < test_bram.v > ${id}.v
 	sed -e "s/ABITS = ./ABITS = $abits/g; s/DBITS = ./DBITS = $dbits/g;" < test_bram_tb.v > ${id}_tb.v
 	../../../yosys -ql ${id}_syn.log -p "synth_ice40" -o ${id}_syn.v ${id}.v
-	iverilog -s bram_tb -o ${id}_tb ${id}_syn.v ${id}_tb.v /opt/lscc/iCEcube2.2014.08/verilog/sb_ice_syn.v
-	# iverilog -s bram_tb -o ${id}_tb ${id}_syn.v ${id}_tb.v ../cells_sim.v
+	# iverilog -s bram_tb -o ${id}_tb ${id}_syn.v ${id}_tb.v /opt/lscc/iCEcube2.2014.08/verilog/sb_ice_syn.v
+	iverilog -s bram_tb -o ${id}_tb ${id}_syn.v ${id}_tb.v ../cells_sim.v
 	./${id}_tb > ${id}_tb.txt
-	if grep ERROR ${id}_tb.txt; then false; fi
+	if grep -H ERROR ${id}_tb.txt; then false; fi
 done; done
 echo OK
 
diff --git a/techlibs/ice40/tests/test_bram_tb.v b/techlibs/ice40/tests/test_bram_tb.v
index 5d9f92228..ade53db03 100644
--- a/techlibs/ice40/tests/test_bram_tb.v
+++ b/techlibs/ice40/tests/test_bram_tb.v
@@ -86,7 +86,7 @@ module bram_tb #(
 			xorshift64_next;
 
 			RD_ADDR = getaddr(i < 256 ? i[3:0] : xorshift64_state[59:56]);
-			WR_EN = xorshift64_state[55] && (WR_ADDR != RD_ADDR);
+			WR_EN = xorshift64_state[55] && ((WR_ADDR & 'hff) != (RD_ADDR & 'hff));
 			xorshift64_next;
 
 			#1; clk <= 1;