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| author | Sean Anderson <seanga2@gmail.com> | 2022-05-18 14:53:46 -0400 |
|---|---|---|
| committer | Sean Anderson <seanga2@gmail.com> | 2022-08-09 23:42:24 -0400 |
| commit | 8c05f14b58fd0d4d6409342a172cd73202e507ae (patch) | |
| tree | cd73d205f48c802af02890373596007e786dbdba /techlibs/ice40/tests | |
| parent | 035d99f3a82812669b801fb27aeee30876d61049 (diff) | |
| download | yosys-8c05f14b58fd0d4d6409342a172cd73202e507ae.tar.gz yosys-8c05f14b58fd0d4d6409342a172cd73202e507ae.tar.bz2 yosys-8c05f14b58fd0d4d6409342a172cd73202e507ae.zip | |
Order ports with default assignments first
Although the current style is allowed by the standard, Icarus verilog
doesn't parse default assignments using an implicit net type:
techlibs/ice40/cells_sim.v:305: syntax error
techlibs/ice40/cells_sim.v:1: Errors in port declarations.
Fix this by making sure that ports with default assignments first on
their line.
Fixes: 46d3f03d2 ("Add default assignments to other SB_* simulation models")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Diffstat (limited to 'techlibs/ice40/tests')
0 files changed, 0 insertions, 0 deletions