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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 20:18:17 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 20:18:17 -0700 |
| commit | b7a48e3e0f49f09e12a2b394b62256a87c398dbc (patch) | |
| tree | 9667249b7e1ab86c264f44d0a2f03b326e2763fa /techlibs/ice40/tests | |
| parent | c320abc3f490b09b21804581c2b386c30d186a1e (diff) | |
| parent | 33960dd3d84b628f6e5de45c112368dc80626457 (diff) | |
| download | yosys-b7a48e3e0f49f09e12a2b394b62256a87c398dbc.tar.gz yosys-b7a48e3e0f49f09e12a2b394b62256a87c398dbc.tar.bz2 yosys-b7a48e3e0f49f09e12a2b394b62256a87c398dbc.zip | |
Merge remote-tracking branch 'origin/master' into xc7dsp
Diffstat (limited to 'techlibs/ice40/tests')
| -rw-r--r-- | techlibs/ice40/tests/test_arith.ys | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/techlibs/ice40/tests/test_arith.ys b/techlibs/ice40/tests/test_arith.ys index 160c767fb..ddb80b700 100644 --- a/techlibs/ice40/tests/test_arith.ys +++ b/techlibs/ice40/tests/test_arith.ys @@ -1,6 +1,5 @@ read_verilog test_arith.v synth_ice40 -techmap -map ../cells_sim.v rename test gate read_verilog test_arith.v @@ -8,3 +7,11 @@ rename test gold miter -equiv -flatten -make_outputs gold gate miter sat -verify -prove trigger 0 -show-ports miter + +synth_ice40 -top gate + +read_verilog test_arith.v +rename test gold + +miter -equiv -flatten -make_outputs gold gate miter +sat -verify -prove trigger 0 -show-ports miter |