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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-05 04:02:42 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-13 19:21:05 +0200 |
| commit | 3209c0762a560d68ce7aef00942a8b3e440d5a61 (patch) | |
| tree | a51aafdf7abd7f791a30297eb35382c540d41c6b /techlibs/intel/Makefile.inc | |
| parent | a3a90f6377f251d3b6c5898eb1543f8832493bb8 (diff) | |
| download | yosys-3209c0762a560d68ce7aef00942a8b3e440d5a61.tar.gz yosys-3209c0762a560d68ce7aef00942a8b3e440d5a61.tar.bz2 yosys-3209c0762a560d68ce7aef00942a8b3e440d5a61.zip | |
intel: Use dfflegalize.
Diffstat (limited to 'techlibs/intel/Makefile.inc')
| -rw-r--r-- | techlibs/intel/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/techlibs/intel/Makefile.inc b/techlibs/intel/Makefile.inc index f751e341f..fef6aab77 100644 --- a/techlibs/intel/Makefile.inc +++ b/techlibs/intel/Makefile.inc @@ -5,6 +5,7 @@ $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/m9k_bb.v)) $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/altpll_bb.v)) $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_m9k.txt)) $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_m9k.v)) +$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/ff_map.v)) # Add the cell models and mappings for the VQM backend families := max10 arria10gx cyclonev cyclone10lp cycloneiv cycloneive |