aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/intel/Makefile.inc
diff options
context:
space:
mode:
authorDavid Shah <dave@ds0.me>2019-08-30 13:57:15 +0100
committerDavid Shah <dave@ds0.me>2019-08-30 13:57:15 +0100
commit6919c0f9b010c94a0a1a31cd788301e78a1bcbfb (patch)
tree4780799b6c1dc1d150b80aa142e6c53e06760cb3 /techlibs/intel/Makefile.inc
parentedff79a25a802e5b1816608b48e3ac335ad87147 (diff)
parent694e30a35426b9582a1f2db730528d4d34305795 (diff)
downloadyosys-6919c0f9b010c94a0a1a31cd788301e78a1bcbfb.tar.gz
yosys-6919c0f9b010c94a0a1a31cd788301e78a1bcbfb.tar.bz2
yosys-6919c0f9b010c94a0a1a31cd788301e78a1bcbfb.zip
Merge branch 'master' into xc7dsp
Diffstat (limited to 'techlibs/intel/Makefile.inc')
-rw-r--r--techlibs/intel/Makefile.inc20
1 files changed, 5 insertions, 15 deletions
diff --git a/techlibs/intel/Makefile.inc b/techlibs/intel/Makefile.inc
index 7a3d2c71a..4e8f423c8 100644
--- a/techlibs/intel/Makefile.inc
+++ b/techlibs/intel/Makefile.inc
@@ -5,20 +5,10 @@ $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/m9k_bb.v))
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/altpll_bb.v))
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_m9k.txt))
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_m9k.v))
-$(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/cells_sim.v))
-$(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/cells_sim.v))
-$(eval $(call add_share_file,share/intel/cyclonev,techlibs/intel/cyclonev/cells_sim.v))
-$(eval $(call add_share_file,share/intel/cyclone10,techlibs/intel/cyclone10/cells_sim.v))
-$(eval $(call add_share_file,share/intel/cycloneiv,techlibs/intel/cycloneiv/cells_sim.v))
-$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/cells_sim.v))
-$(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/cells_map.v))
-$(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/cells_map.v))
-$(eval $(call add_share_file,share/intel/cyclonev,techlibs/intel/cyclonev/cells_map.v))
-$(eval $(call add_share_file,share/intel/cyclone10,techlibs/intel/cyclone10/cells_map.v))
-$(eval $(call add_share_file,share/intel/cycloneiv,techlibs/intel/cycloneiv/cells_map.v))
-$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/cells_map.v))
-#$(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/arith_map.v))
-#$(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/arith_map.v))
-#$(eval $(call add_share_file,share/intel/cycloneiv,techlibs/intel/cycloneiv/arith_map.v))
+
+# Add the cell models and mappings for the VQM backend
+families := max10 a10gx cyclonev cyclone10 cycloneiv cycloneive
+$(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_sim.v)))
+$(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_map.v)))
#$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/arith_map.v))