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author | Eddie Hung <eddie@fpgeh.com> | 2019-07-25 10:49:26 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-25 10:49:26 -0700 |
commit | a02d1720a766ae1b993a9884e840f37b3d785b8f (patch) | |
tree | d11cde6c9cb30afc8a54d49834d79facf94bb5a7 /techlibs/intel/Makefile.inc | |
parent | c5e31ac9c3c49f38ddcb6e613ef4a092d69f71a2 (diff) | |
parent | eb663c75794d1249247ba88bf0bee835c98a8a85 (diff) | |
download | yosys-a02d1720a766ae1b993a9884e840f37b3d785b8f.tar.gz yosys-a02d1720a766ae1b993a9884e840f37b3d785b8f.tar.bz2 yosys-a02d1720a766ae1b993a9884e840f37b3d785b8f.zip |
Merge branch 'master' of github.com:YosysHQ/yosys
Diffstat (limited to 'techlibs/intel/Makefile.inc')
-rw-r--r-- | techlibs/intel/Makefile.inc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/intel/Makefile.inc b/techlibs/intel/Makefile.inc index ec7cea379..7a3d2c71a 100644 --- a/techlibs/intel/Makefile.inc +++ b/techlibs/intel/Makefile.inc @@ -3,8 +3,8 @@ OBJS += techlibs/intel/synth_intel.o $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/m9k_bb.v)) $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/altpll_bb.v)) -$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams.txt)) -$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map.v)) +$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_m9k.txt)) +$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_m9k.v)) $(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/cells_sim.v)) $(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/cells_sim.v)) $(eval $(call add_share_file,share/intel/cyclonev,techlibs/intel/cyclonev/cells_sim.v)) |