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| author | Diego H <diego@symbioticeda.com> | 2019-12-12 13:40:05 -0600 |
|---|---|---|
| committer | Diego H <diego@symbioticeda.com> | 2019-12-12 13:40:05 -0600 |
| commit | ab6ac8327f28b2ba9530c81cdbb5091a1ef91032 (patch) | |
| tree | 9e2716d6d621eeeda85896b7b2993de517bb931a /techlibs/intel/Makefile.inc | |
| parent | 3a5a65829cc593965304537ddcb4d6d1d3e3ca8b (diff) | |
| parent | 2666482282421bb54213ba01054111eadc401373 (diff) | |
| download | yosys-ab6ac8327f28b2ba9530c81cdbb5091a1ef91032.tar.gz yosys-ab6ac8327f28b2ba9530c81cdbb5091a1ef91032.tar.bz2 yosys-ab6ac8327f28b2ba9530c81cdbb5091a1ef91032.zip | |
Merge https://github.com/YosysHQ/yosys into bram_xilinx
Diffstat (limited to 'techlibs/intel/Makefile.inc')
| -rw-r--r-- | techlibs/intel/Makefile.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/intel/Makefile.inc b/techlibs/intel/Makefile.inc index 4e8f423c8..d97a9b58f 100644 --- a/techlibs/intel/Makefile.inc +++ b/techlibs/intel/Makefile.inc @@ -7,7 +7,7 @@ $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_m9k. $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_m9k.v)) # Add the cell models and mappings for the VQM backend -families := max10 a10gx cyclonev cyclone10 cycloneiv cycloneive +families := max10 arria10gx cyclonev cyclone10lp cycloneiv cycloneive $(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_sim.v))) $(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_map.v))) #$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/arith_map.v)) |