diff options
| author | Clifford Wolf <clifford@clifford.at> | 2017-11-18 09:56:36 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-11-18 09:56:36 +0100 |
| commit | c01df04e32f7913622f40ced56fcb523ac96d35f (patch) | |
| tree | 87bb6d6a666a4246aa90bae9838b82ba62c41574 /techlibs/intel/Makefile.inc | |
| parent | 234726c65537cf665681bf9af5bda6d57a90df23 (diff) | |
| parent | acee813a5c0d5517ea4123945e4971ddd2e5f3a4 (diff) | |
| download | yosys-c01df04e32f7913622f40ced56fcb523ac96d35f.tar.gz yosys-c01df04e32f7913622f40ced56fcb523ac96d35f.tar.bz2 yosys-c01df04e32f7913622f40ced56fcb523ac96d35f.zip | |
Merge pull request #453 from dh73/master
Updating Intel FPGA subsystem with Cyclone 10, minor changes in examples/intel directory and Speedster cells
Diffstat (limited to 'techlibs/intel/Makefile.inc')
| -rw-r--r-- | techlibs/intel/Makefile.inc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/intel/Makefile.inc b/techlibs/intel/Makefile.inc index 429d23677..ec7cea379 100644 --- a/techlibs/intel/Makefile.inc +++ b/techlibs/intel/Makefile.inc @@ -8,11 +8,13 @@ $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map. $(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/cells_sim.v)) $(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/cells_sim.v)) $(eval $(call add_share_file,share/intel/cyclonev,techlibs/intel/cyclonev/cells_sim.v)) +$(eval $(call add_share_file,share/intel/cyclone10,techlibs/intel/cyclone10/cells_sim.v)) $(eval $(call add_share_file,share/intel/cycloneiv,techlibs/intel/cycloneiv/cells_sim.v)) $(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/cells_sim.v)) $(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/cells_map.v)) $(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/cells_map.v)) $(eval $(call add_share_file,share/intel/cyclonev,techlibs/intel/cyclonev/cells_map.v)) +$(eval $(call add_share_file,share/intel/cyclone10,techlibs/intel/cyclone10/cells_map.v)) $(eval $(call add_share_file,share/intel/cycloneiv,techlibs/intel/cycloneiv/cells_map.v)) $(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/cells_map.v)) #$(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/arith_map.v)) |