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| author | Clifford Wolf <clifford@clifford.at> | 2017-10-10 15:16:45 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-10-10 15:16:45 +0200 |
| commit | 12c10892e6783e0a1ef52776c232dd342745543f (patch) | |
| tree | 52482dfe8d609403b743698116e889599a5f19db /techlibs/intel/a10gx/cells_arith.v | |
| parent | c10e96c9ec8c4e56935ba796af0fa3d1f22b2a71 (diff) | |
| parent | 7c57d8fbb44cdc466f4e384528109ada7e52b4c1 (diff) | |
| download | yosys-12c10892e6783e0a1ef52776c232dd342745543f.tar.gz yosys-12c10892e6783e0a1ef52776c232dd342745543f.tar.bz2 yosys-12c10892e6783e0a1ef52776c232dd342745543f.zip | |
Merge branch 'master' of github.com:cliffordwolf/yosys
Diffstat (limited to 'techlibs/intel/a10gx/cells_arith.v')
| -rw-r--r--[-rwxr-xr-x] | techlibs/intel/a10gx/cells_arith.v | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/intel/a10gx/cells_arith.v b/techlibs/intel/a10gx/cells_arith.v index 470b686bb..89fb4561f 100755..100644 --- a/techlibs/intel/a10gx/cells_arith.v +++ b/techlibs/intel/a10gx/cells_arith.v @@ -45,10 +45,10 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO); //wire [Y_WIDTH:0] C = {CO, CI}; wire [Y_WIDTH+1:0] COx; wire [Y_WIDTH+1:0] C = {COx, CI}; - + /* Start implementation */ (* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1)); - + genvar i; generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice if(i==Y_WIDTH-1) begin @@ -61,5 +61,5 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO); endgenerate /* End implementation */ assign X = AA ^ BB; - -endmodule + +endmodule |