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| author | Clifford Wolf <clifford@clifford.at> | 2017-10-10 15:16:45 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-10-10 15:16:45 +0200 |
| commit | 12c10892e6783e0a1ef52776c232dd342745543f (patch) | |
| tree | 52482dfe8d609403b743698116e889599a5f19db /techlibs/intel/a10gx/cells_map.v | |
| parent | c10e96c9ec8c4e56935ba796af0fa3d1f22b2a71 (diff) | |
| parent | 7c57d8fbb44cdc466f4e384528109ada7e52b4c1 (diff) | |
| download | yosys-12c10892e6783e0a1ef52776c232dd342745543f.tar.gz yosys-12c10892e6783e0a1ef52776c232dd342745543f.tar.bz2 yosys-12c10892e6783e0a1ef52776c232dd342745543f.zip | |
Merge branch 'master' of github.com:cliffordwolf/yosys
Diffstat (limited to 'techlibs/intel/a10gx/cells_map.v')
| -rw-r--r--[-rwxr-xr-x] | techlibs/intel/a10gx/cells_map.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/intel/a10gx/cells_map.v b/techlibs/intel/a10gx/cells_map.v index 42e7926b8..1430e8551 100755..100644 --- a/techlibs/intel/a10gx/cells_map.v +++ b/techlibs/intel/a10gx/cells_map.v @@ -31,13 +31,13 @@ module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; input [WIDTH-1:0] A; - output Y; + output Y; generate if (WIDTH == 1) begin assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function end else if (WIDTH == 2) begin - twentynm_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off")) + twentynm_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1), .datae(1'b1), .dataf(1'b1), .datag(1'b1)); end /*else if(WIDTH == 3) begin |