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| author | Clifford Wolf <clifford@clifford.at> | 2017-10-10 15:16:45 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-10-10 15:16:45 +0200 |
| commit | 12c10892e6783e0a1ef52776c232dd342745543f (patch) | |
| tree | 52482dfe8d609403b743698116e889599a5f19db /techlibs/intel/a10gx/cells_sim.v | |
| parent | c10e96c9ec8c4e56935ba796af0fa3d1f22b2a71 (diff) | |
| parent | 7c57d8fbb44cdc466f4e384528109ada7e52b4c1 (diff) | |
| download | yosys-12c10892e6783e0a1ef52776c232dd342745543f.tar.gz yosys-12c10892e6783e0a1ef52776c232dd342745543f.tar.bz2 yosys-12c10892e6783e0a1ef52776c232dd342745543f.zip | |
Merge branch 'master' of github.com:cliffordwolf/yosys
Diffstat (limited to 'techlibs/intel/a10gx/cells_sim.v')
| -rw-r--r--[-rwxr-xr-x] | techlibs/intel/a10gx/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/intel/a10gx/cells_sim.v b/techlibs/intel/a10gx/cells_sim.v index 1888682ef..e892b377e 100755..100644 --- a/techlibs/intel/a10gx/cells_sim.v +++ b/techlibs/intel/a10gx/cells_sim.v @@ -38,7 +38,7 @@ endmodule // twentynm_io_obuf /* Altera Arria 10 GX LUT Primitive */ module twentynm_lcell_comb (output combout, cout, sumout, - input dataa, datab, datac, datad, + input dataa, datab, datac, datad, input datae, dataf, datag, cin, input sharein); |