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| author | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2017-10-04 17:01:30 -0700 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-10-05 16:23:49 +0200 |
| commit | 50bcd9a728ff89f220873b3345c4e18a65c4a37f (patch) | |
| tree | ff7b306d49b46ec25b7bfac26ca9ace82302a3f0 /techlibs/intel/a10gx/cells_sim.v | |
| parent | fc3378916dbaf46018a99571ef190189088c225c (diff) | |
| download | yosys-50bcd9a728ff89f220873b3345c4e18a65c4a37f.tar.gz yosys-50bcd9a728ff89f220873b3345c4e18a65c4a37f.tar.bz2 yosys-50bcd9a728ff89f220873b3345c4e18a65c4a37f.zip | |
Clean whitespace and permissions in techlibs/intel
Diffstat (limited to 'techlibs/intel/a10gx/cells_sim.v')
| -rw-r--r--[-rwxr-xr-x] | techlibs/intel/a10gx/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/intel/a10gx/cells_sim.v b/techlibs/intel/a10gx/cells_sim.v index 1888682ef..e892b377e 100755..100644 --- a/techlibs/intel/a10gx/cells_sim.v +++ b/techlibs/intel/a10gx/cells_sim.v @@ -38,7 +38,7 @@ endmodule // twentynm_io_obuf /* Altera Arria 10 GX LUT Primitive */ module twentynm_lcell_comb (output combout, cout, sumout, - input dataa, datab, datac, datad, + input dataa, datab, datac, datad, input datae, dataf, datag, cin, input sharein); |