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| author | Clifford Wolf <clifford@clifford.at> | 2017-10-10 15:16:45 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-10-10 15:16:45 +0200 |
| commit | 12c10892e6783e0a1ef52776c232dd342745543f (patch) | |
| tree | 52482dfe8d609403b743698116e889599a5f19db /techlibs/intel/common/altpll_bb.v | |
| parent | c10e96c9ec8c4e56935ba796af0fa3d1f22b2a71 (diff) | |
| parent | 7c57d8fbb44cdc466f4e384528109ada7e52b4c1 (diff) | |
| download | yosys-12c10892e6783e0a1ef52776c232dd342745543f.tar.gz yosys-12c10892e6783e0a1ef52776c232dd342745543f.tar.bz2 yosys-12c10892e6783e0a1ef52776c232dd342745543f.zip | |
Merge branch 'master' of github.com:cliffordwolf/yosys
Diffstat (limited to 'techlibs/intel/common/altpll_bb.v')
| -rw-r--r-- | techlibs/intel/common/altpll_bb.v | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/intel/common/altpll_bb.v b/techlibs/intel/common/altpll_bb.v index 27eef0f86..d2e6a3643 100644 --- a/techlibs/intel/common/altpll_bb.v +++ b/techlibs/intel/common/altpll_bb.v @@ -19,7 +19,7 @@ /* No clearbox model */ `ifdef NO_CLEARBOX (* blackbox *) -module altpll +module altpll ( inclk, fbin, pllena, @@ -62,7 +62,7 @@ module altpll c2, c3, c4); - + parameter intended_device_family = "MAX 10"; parameter operation_mode = "NORMAL"; parameter pll_type = "AUTO"; @@ -340,7 +340,7 @@ module altpll input phasestep; input configupdate; inout fbmimicbidir; - + output [width_clock-1:0] clk; output [3:0] extclk; @@ -361,6 +361,6 @@ module altpll output fref; output icdrclk; output c0, c1, c2, c3, c4; - + endmodule // altpll `endif |