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| author | Clifford Wolf <clifford@clifford.at> | 2017-10-03 17:33:43 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-10-03 17:33:43 +0200 |
| commit | b4fd7ecd839af207e8c332d8f37a59b6c0196b9d (patch) | |
| tree | 866f50f10a644202612aecce5ca07e48dec35102 /techlibs/intel/common/brams.txt | |
| parent | c5b204d8d283d16e6eae8658034da6d378b6810e (diff) | |
| parent | 65f91e51205fdd436c569c4795517160960ac700 (diff) | |
| download | yosys-b4fd7ecd839af207e8c332d8f37a59b6c0196b9d.tar.gz yosys-b4fd7ecd839af207e8c332d8f37a59b6c0196b9d.tar.bz2 yosys-b4fd7ecd839af207e8c332d8f37a59b6c0196b9d.zip | |
Merge branch 'dh73-master'
Diffstat (limited to 'techlibs/intel/common/brams.txt')
| -rwxr-xr-x | techlibs/intel/common/brams.txt | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/techlibs/intel/common/brams.txt b/techlibs/intel/common/brams.txt new file mode 100755 index 000000000..3bf21afc9 --- /dev/null +++ b/techlibs/intel/common/brams.txt @@ -0,0 +1,33 @@ +bram $__M9K_ALTSYNCRAM_SINGLEPORT_FULL + init 1 + abits 13 @M1 + dbits 1 @M1 + abits 12 @M2 + dbits 2 @M2 + abits 11 @M3 + dbits 4 @M3 + abits 10 @M4 + dbits 8 @M4 + abits 10 @M5 + dbits 9 @M5 + abits 9 @M6 + dbits 16 @M6 + abits 9 @M7 + dbits 18 @M7 + abits 8 @M8 + dbits 32 @M8 + abits 8 @M9 + dbits 36 @M9 + groups 2 + ports 1 1 + wrmode 0 1 + enable 1 1 + transp 0 0 + clocks 2 3 + clkpol 2 3 +endbram + +match $__M9K_ALTSYNCRAM_SINGLEPORT_FULL + min efficiency 2 + make_transp +endmatch |