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author | Benedikt Tutzer <benedikt.tutzer@tuwien.ac.at> | 2019-03-28 12:16:39 +0100 |
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committer | Benedikt Tutzer <benedikt.tutzer@tuwien.ac.at> | 2019-03-28 12:16:39 +0100 |
commit | 03d1606b42110f8eac7311ac57c7334d1f781273 (patch) | |
tree | 9fc490a93fbb75ac3e23b276a151e22ca1a3b84e /techlibs/intel/common/brams_map.v | |
parent | b9288b216dce110ad11eb0615a6a911a9fcae05b (diff) | |
parent | 32bd0f22ec93202e67395901cdc64c20df7f0da7 (diff) | |
download | yosys-03d1606b42110f8eac7311ac57c7334d1f781273.tar.gz yosys-03d1606b42110f8eac7311ac57c7334d1f781273.tar.bz2 yosys-03d1606b42110f8eac7311ac57c7334d1f781273.zip |
Merge remote-tracking branch 'origin/master' into feature/python_bindings
Diffstat (limited to 'techlibs/intel/common/brams_map.v')
-rw-r--r-- | techlibs/intel/common/brams_map.v | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/techlibs/intel/common/brams_map.v b/techlibs/intel/common/brams_map.v index fae4af2ab..d0f07c1de 100644 --- a/techlibs/intel/common/brams_map.v +++ b/techlibs/intel/common/brams_map.v @@ -2,8 +2,8 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A parameter CFG_ABITS = 8; parameter CFG_DBITS = 36; - parameter ABITS = "1"; - parameter DBITS = "1"; + parameter ABITS = 1; + parameter DBITS = 1; parameter CLKPOL2 = 1; parameter CLKPOL3 = 1; @@ -63,21 +63,21 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A .width_byteena_a (1), // Forced value .numwords_b ( NUMWORDS ), .numwords_a ( NUMWORDS ), - .widthad_b ( CFG_ABITS ), - .width_b ( CFG_DBITS ), - .widthad_a ( CFG_ABITS ), - .width_a ( CFG_DBITS ) + .widthad_b ( CFG_DBITS ), + .width_b ( CFG_ABITS ), + .widthad_a ( CFG_DBITS ), + .width_a ( CFG_ABITS ) ) _TECHMAP_REPLACE_ ( .data_a(B1DATA), .address_a(B1ADDR), .wren_a(B1EN), .rden_a(A1EN), .q_a(A1DATA), - .data_b(1'b0), + .data_b(B1DATA), .address_b(0), .wren_b(1'b0), .rden_b(1'b0), - .q_b(1'b0), + .q_b(), .clock0(CLK2), .clock1(1'b1), // Unused in single port mode .clocken0(1'b1), |