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| author | Clifford Wolf <clifford@clifford.at> | 2018-12-05 09:08:30 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-12-05 09:08:30 -0800 |
| commit | e1153031291275dc1c16445b1b2089ffd4335845 (patch) | |
| tree | f45dd42d35408b5496b469a9f542a36fcfb08162 /techlibs/intel/common/brams_map.v | |
| parent | 1a260ce89b79f0d4c2092f725b48583bd5e7bc41 (diff) | |
| parent | 819ca7309620b3791c7b93de44990ffb4fceb30f (diff) | |
| download | yosys-e1153031291275dc1c16445b1b2089ffd4335845.tar.gz yosys-e1153031291275dc1c16445b1b2089ffd4335845.tar.bz2 yosys-e1153031291275dc1c16445b1b2089ffd4335845.zip | |
Merge pull request #713 from Diego-HR/master
Changes in GoWin synth commands and ALU primitive support
Diffstat (limited to 'techlibs/intel/common/brams_map.v')
| -rw-r--r-- | techlibs/intel/common/brams_map.v | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/techlibs/intel/common/brams_map.v b/techlibs/intel/common/brams_map.v index fae4af2ab..d0f07c1de 100644 --- a/techlibs/intel/common/brams_map.v +++ b/techlibs/intel/common/brams_map.v @@ -2,8 +2,8 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A parameter CFG_ABITS = 8; parameter CFG_DBITS = 36; - parameter ABITS = "1"; - parameter DBITS = "1"; + parameter ABITS = 1; + parameter DBITS = 1; parameter CLKPOL2 = 1; parameter CLKPOL3 = 1; @@ -63,21 +63,21 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A .width_byteena_a (1), // Forced value .numwords_b ( NUMWORDS ), .numwords_a ( NUMWORDS ), - .widthad_b ( CFG_ABITS ), - .width_b ( CFG_DBITS ), - .widthad_a ( CFG_ABITS ), - .width_a ( CFG_DBITS ) + .widthad_b ( CFG_DBITS ), + .width_b ( CFG_ABITS ), + .widthad_a ( CFG_DBITS ), + .width_a ( CFG_ABITS ) ) _TECHMAP_REPLACE_ ( .data_a(B1DATA), .address_a(B1ADDR), .wren_a(B1EN), .rden_a(A1EN), .q_a(A1DATA), - .data_b(1'b0), + .data_b(B1DATA), .address_b(0), .wren_b(1'b0), .rden_b(1'b0), - .q_b(1'b0), + .q_b(), .clock0(CLK2), .clock1(1'b1), // Unused in single port mode .clocken0(1'b1), |