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| author | Maciej Kurc <mkurc@antmicro.com> | 2019-05-16 12:53:43 +0200 |
|---|---|---|
| committer | Maciej Kurc <mkurc@antmicro.com> | 2019-05-16 12:53:43 +0200 |
| commit | 1f52332b8d4621d6c5ab1447e82b6e2e53600e52 (patch) | |
| tree | 9977477bebc1105ca0cf2b82c79e092faa66d832 /techlibs/intel/common/brams_map_m9k.v | |
| parent | ce4a0954bc896eedfc2d87e2c9d2b40f42a101db (diff) | |
| download | yosys-1f52332b8d4621d6c5ab1447e82b6e2e53600e52.tar.gz yosys-1f52332b8d4621d6c5ab1447e82b6e2e53600e52.tar.bz2 yosys-1f52332b8d4621d6c5ab1447e82b6e2e53600e52.zip | |
Added tests for Verilog frontent for attributes on parameters and localparams
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Diffstat (limited to 'techlibs/intel/common/brams_map_m9k.v')
0 files changed, 0 insertions, 0 deletions