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| author | Clifford Wolf <clifford@clifford.at> | 2017-10-10 15:16:45 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-10-10 15:16:45 +0200 |
| commit | 12c10892e6783e0a1ef52776c232dd342745543f (patch) | |
| tree | 52482dfe8d609403b743698116e889599a5f19db /techlibs/intel/common/m9k_bb.v | |
| parent | c10e96c9ec8c4e56935ba796af0fa3d1f22b2a71 (diff) | |
| parent | 7c57d8fbb44cdc466f4e384528109ada7e52b4c1 (diff) | |
| download | yosys-12c10892e6783e0a1ef52776c232dd342745543f.tar.gz yosys-12c10892e6783e0a1ef52776c232dd342745543f.tar.bz2 yosys-12c10892e6783e0a1ef52776c232dd342745543f.zip | |
Merge branch 'master' of github.com:cliffordwolf/yosys
Diffstat (limited to 'techlibs/intel/common/m9k_bb.v')
| -rw-r--r--[-rwxr-xr-x] | techlibs/intel/common/m9k_bb.v | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/techlibs/intel/common/m9k_bb.v b/techlibs/intel/common/m9k_bb.v index 4370a105e..b18a752f5 100755..100644 --- a/techlibs/intel/common/m9k_bb.v +++ b/techlibs/intel/common/m9k_bb.v @@ -17,10 +17,10 @@ * */ (* blackbox *) -module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wren_b, rden_b, - q_b, clock0, clock1, clocken0, clocken1, clocken2, clocken3, aclr0, aclr1, +module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wren_b, rden_b, + q_b, clock0, clock1, clocken0, clocken1, clocken2, clocken3, aclr0, aclr1, addressstall_a, addressstall_b); - + parameter clock_enable_input_b = "ALTERNATE"; parameter clock_enable_input_a = "ALTERNATE"; parameter clock_enable_output_b = "NORMAL"; @@ -33,7 +33,7 @@ module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wr parameter operation_mode = "SINGLE_PORT"; parameter intended_device_family = "MAX 10 FPGA"; parameter outdata_reg_a = "UNREGISTERED"; - parameter lpm_type = "altsyncram"; + parameter lpm_type = "altsyncram"; parameter init_type = "unused"; parameter ram_block_type = "AUTO"; parameter lpm_hint = "ENABLE_RUNTIME_MOD=NO"; @@ -46,7 +46,7 @@ module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wr parameter width_b = 1; parameter widthad_a = 1; parameter width_a = 1; - + // Port A declarations output [35:0] q_a; input [35:0] data_a; @@ -66,5 +66,5 @@ module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wr input addressstall_a; input addressstall_b; // TODO: Implement the correct simulation model - + endmodule // altsyncram |