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| author | dh73 <dh73_fpga@qq.com> | 2017-10-01 19:59:45 -0500 |
|---|---|---|
| committer | dh73 <dh73_fpga@qq.com> | 2017-10-01 19:59:45 -0500 |
| commit | 4718e65763854d9870bf9b88a7c1b1e78e10f05f (patch) | |
| tree | f6c08700f180d2f4475bd57341c578a37184b304 /techlibs/intel/common/m9k_bb.v | |
| parent | e4808477531d31284244188637af3ccf89a21269 (diff) | |
| download | yosys-4718e65763854d9870bf9b88a7c1b1e78e10f05f.tar.gz yosys-4718e65763854d9870bf9b88a7c1b1e78e10f05f.tar.bz2 yosys-4718e65763854d9870bf9b88a7c1b1e78e10f05f.zip | |
Tested and working altsyncarm without init files
Diffstat (limited to 'techlibs/intel/common/m9k_bb.v')
| -rwxr-xr-x | techlibs/intel/common/m9k_bb.v | 46 |
1 files changed, 25 insertions, 21 deletions
diff --git a/techlibs/intel/common/m9k_bb.v b/techlibs/intel/common/m9k_bb.v index cf178db63..4370a105e 100755 --- a/techlibs/intel/common/m9k_bb.v +++ b/techlibs/intel/common/m9k_bb.v @@ -21,27 +21,31 @@ module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wr q_b, clock0, clock1, clocken0, clocken1, clocken2, clocken3, aclr0, aclr1, addressstall_a, addressstall_b); - parameter clock_enable_input_b = "ALTERNATE"; - parameter clock_enable_input_a = "ALTERNATE"; - parameter clock_enable_output_b = "NORMAL"; - parameter clock_enable_output_a = "NORMAL"; - parameter wrcontrol_aclr_a = "NONE"; - parameter indata_aclr_a = "NONE"; - parameter address_aclr_a = "NONE"; - parameter outdata_aclr_a = "NONE"; - parameter outdata_reg_a = "UNREGISTERED"; - parameter operation_mode = "SINGLE_PORT"; - parameter intended_device_family = "MAX 10 FPGA"; - parameter outdata_reg_a = "UNREGISTERED"; - parameter lpm_type = "altsyncram"; - parameter init_type = "unused"; - parameter ram_block_type = "AUTO"; - parameter numwords_b = 0; - parameter numwords_a = 0; - parameter widthad_b = 1; - parameter width_b = 1; - parameter widthad_a = 1; - parameter width_a = 1; + parameter clock_enable_input_b = "ALTERNATE"; + parameter clock_enable_input_a = "ALTERNATE"; + parameter clock_enable_output_b = "NORMAL"; + parameter clock_enable_output_a = "NORMAL"; + parameter wrcontrol_aclr_a = "NONE"; + parameter indata_aclr_a = "NONE"; + parameter address_aclr_a = "NONE"; + parameter outdata_aclr_a = "NONE"; + parameter outdata_reg_a = "UNREGISTERED"; + parameter operation_mode = "SINGLE_PORT"; + parameter intended_device_family = "MAX 10 FPGA"; + parameter outdata_reg_a = "UNREGISTERED"; + parameter lpm_type = "altsyncram"; + parameter init_type = "unused"; + parameter ram_block_type = "AUTO"; + parameter lpm_hint = "ENABLE_RUNTIME_MOD=NO"; + parameter power_up_uninitialized = "FALSE"; + parameter read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ"; + parameter width_byteena_a = 1; + parameter numwords_b = 0; + parameter numwords_a = 0; + parameter widthad_b = 1; + parameter width_b = 1; + parameter widthad_a = 1; + parameter width_a = 1; // Port A declarations output [35:0] q_a; |